The present invention relates to microelectronic packaging.
A typical semiconductor chip is formed as a generally thin, rectangular solid having front and rear major surfaces and small edge surfaces extending between the front and rear surfaces. The thickness or distance between the front and rear surfaces of the chip typically is many times smaller than the length and width of the chip measured in the plane of the front surface or rear surface. The chip typically has contacts on its front surface and electronic circuitry within the chip connected to the contacts. In use, the contacts are electrically connected to a larger circuit. Ordinarily, chips are manufactured by treating a larger, flat wafer to form the electronic circuitry and contacts of numerous chips simultaneously, and then severing the wafer along lines referred to as “dicing lanes” which form the edges or boundaries of the individual chips.
Chips typically are mounted in structures referred to as packages. A package may include a package substrate such as a small circuit panel having terminals thereon. The chip is physically attached to the package substrate, and the contacts of the chip are electrically connected to the terminals of the package substrate. The package substrate, with or without other components, provides physical protection for the chip. Moreover, the terminals of the package substrate are arranged so that the package as a whole can be readily mounted to a circuit panel or other structure to provide the interconnection between the chip and the larger circuit. Many chip packages have terminals that may be larger than the contacts of the chip, spaced apart from one another at larger intervals than the contacts of the chip, or both, so that the terminals can be soldered readily to conductive structures on a larger circuit panel using standard bonding techniques such as surface mounting. For example, the terminals on a chip package may be arranged in a pattern corresponding to a formal or informal industry standard such as those published by the JEDEC Solid State Technology Association.
Certain semiconductor chips are provided with their contacts disposed in one or more columns extending in a column direction along the front face of the chip. Typically, the column direction is parallel to two edges of the chip. For example, the column or columns of contacts may be disposed midway between the left and right edges of the chip and may be parallel to the edges of the chip. Memory chips such as dynamic random access memory (“DRAM”) chips commonly are provided in this configuration. Chips of this type commonly are packaged using a package substrate having upper and lower surfaces, terminals at the lower surface, and an aperture in the form of an elongated slot extending through the substrate from the upper surface to the lower surface. The substrate may have bond pads at the lower surface adjacent the slot, the bond pads being electrically connected to the terminals by traces on the package substrate. The chip is mounted to the upper surface of the package substrate with the front face of the chip facing downwardly toward the package substrate and with the column or columns of contacts on the chip aligned with the slot in the package substrate. The contacts of the chip are connected to the bond pads of the package substrate by wire bonds extending through the slot in the package substrate, so that the contacts of the chip are electrically connected to the terminals of the package substrate. The wire bonds typically are covered by an encapsulant, which fills the slot. The terminals at the lower surface of the package substrate can be bonded to contact pads on a circuit panel so that the chip is interconnected with a larger circuit incorporated in the circuit panel.
Some semiconductor packages contain multiple chips in a stacked configuration and may occupy an area on the circuit board that is the same as, or only slightly larger than, a package containing a single chip of the same type. This conserves space on the circuit board. Moreover, stacking plural chips in a package reduces the number of packages that must be mounted to the circuit board to form the completed circuit and, therefore, can reduce the cost of the final product. It is often possible to connect corresponding contacts of the plural chips in a stacked configuration to a common terminal on the package. For example, with almost all chips, the power and ground contacts of plural chips can be connected to common power and ground terminals on the package substrate. Memory chips such as DRAM chips typically have numerous contacts in addition to the power and ground contacts which can be connected in common. For example, typical DRAM chips utilize address and command contacts, which are arranged so that the corresponding address and command terminals of plural chips can be connected together to receive the same signals during operation. Each chip typically has some other contacts which must be connected to unique terminals on the package substrate which are not shared with contacts on other chips. For example, where a package contains memory chips, one or more contacts on each chip may be arranged to receive chip select signals designating a particular chip as the recipient of a read or write command.
Connecting corresponding contacts of plural chips in a package to common terminals on the package substrate reduces the total number of terminals required on the package substrate. If each chip in a stack has N contacts, the number of terminals on a package substrate carrying two chips in stacked configuration can be considerably less than 2N. This is advantageous, inasmuch as it saves space and simplifies the package substrate and the mating circuit board.
One type of stacked package incorporates a bottom chip having its front face facing downwardly toward the package substrate and its rear face facing upwardly, away from the package substrate. A top chip is disposed over the bottom chip. The rear face of the top chip faces downwardly, whereas the front face of the top chip faces upwardly, so that the top and bottom chips are arranged in rear face-to-rear face or “back-to-back” configuration. Where both chips in the stack have columns of contacts disposed adjacent the middle of their respective front surfaces, as in the DRAM chips discussed above, the bottom chip can be electrically connected to the terminals of the package substrate using wire bonds extending through an elongated slot in the package substrate to bond pads adjacent the slot in the same manner as discussed above. The upwardly facing contacts of the top chip can be connected to the package substrate by wire bonds, which extend from the contacts of the top chip, over the front face of the top chip and past the edges of the top chip, and extend downwardly adjacent the edges of the stacked chips. These wire bonds join additional bond pads on the package substrate disposed near the edges of the bottom chip. The additional bond pads are also connected to terminals on the package substrate by conductive traces on the substrate.
Where each chip has two or more columns of contacts, including a left column and a right column, a problem arises due to the opposite orientations of the two chips in the stack. The top chip, which is disposed in a front face up orientation, has the left column of contacts disposed to the left in the frame of reference of the package substrate and has the right column of contacts disposed to the right in the same frame of reference. Stated another way, the left column of contacts of the top chip lies closer to the left edge of the substrate, whereas the right column of contacts of the top chip lies closer to the right edge of the substrate. The bottom chip, however, is in an inverted, front face down orientation. Thus, the left column of contacts of the bottom chip lies closer to the right edge of the package substrate, whereas the right column of contacts lies closer to the left edge of the package substrate. The wire bonds from the contacts of the right column in the bottom chip will land at bond pads along the left edge of the slot. It is difficult to provide traces on the package substrate that cross the slot. Therefore the contacts of the right column of contacts on the bottom chip must be connected to terminals disposed between the slot and the left edge of the substrate. Conversely, the contacts of the bottom chip left column will be connected to terminals disposed between the right edge of the slot and the right edge of the substrate.
If corresponding contacts of the two chips are to be connected to common terminals on the package substrate, at least some of the wire bonds emanating from the left column of contacts on the top chip must pass to the right over the front face of the top chip and must cross the right edge of the top chip and connect to bond pads adjacent the right edge of the package substrate. Conversely, at least some wire bonds emanating from the contacts in the right column on the top chip must pass over the left edge of the top chip and join traces adjacent the left edge of the substrate. This implies that the wire bonds emanating from at least some of the contacts on the top chip will cross one another. Such an arrangement can introduce reliability problems, particularly where the wire bonds are closely spaced in the column direction. The wire bonds can be displaced in the column direction as, for example, by encapsulant applied to cover the wire bonds during manufacture. Such displacement can push one wire bond into contact with an adjacent, crossing wire bond. Such contact can lead to misrouted signals and render the packaged chips inoperative. Thus, further improvement would be desirable.